1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a mixed-mode semiconductor device by a simplified fabrication process.
2. Description of the Related Art
In the conventional fabrication process for forming a mixed mode semiconductor device having a capacitor and a gate, the silicon substrate and the polysilicon layer are oxidized by the same thermal oxidation process to form a gate oxide layer on the substrate and an inter-poly oxide layer on the polysilicon layer, respectively. Since the silicon lattice structures of the silicon substrate and the polysilicon layer are different, a thickness ratio about 1 to 2 is resulted instead of obtaining an identical thickness of the gate oxide layer and the inter-poly oxide layer. While fabricating a capacitor, two polysilicon layers are required for forming a top and a bottom electrodes. An etching process is performed to removed a part of these two polysilicon layers. The fabrication process is lengthy and complicated, so that a great fabrication cost is caused.
FIG. 1A to FIG. 1H show a conventional fabrication process for a mix-mode semiconductor device.
In FIG. 1A, a substrate 100 having a field oxide layer 101 and a device active region 102 thereon is provided. The active region 102 is covered by an oxide layer 104. A conformal polysilicon layer 103 is formed on the oxide layer 104 and the field oxide layer 101. A photo-resist layer 105 is formed on the polysilicon layer 104 at a position predetermined for forming a capacitor in the subsequent processes.
In FIG. 1B, the polysilicon layer 104 is etched with the photo-resist layer 105 as a mask until the field oxide layer 101 is exposed, so that a bottom electrode 103a is formed.
In FIG. 1C, the oxide layer 104 is removed. Using thermal oxidation, a gate oxide layer 107 is formed on the active region 102, while an inter-poly oxide layer 106 is formed to cover the bottom electrode 103a.
In FIG. 1D, a conformal polysilicon layer 108 is formed to cover the gate oxide layer 107, the field oxide layer 101, and the inter-poly oxide layer 106.
In FIG. 1E, a conformal tungsten silicide layer 110 is formed on the polysilicon layer 108.
In FIG. 1F, a patterned photo-resist layer 112 is formed on the tungsten silicide layer 110. The areas covered by the photo-resist layer 112 are predetermined as positions for forming a gate and top electrode.
In FIG. 1G, the tungsten silicide layer 110 is etched with the photo-resist layer 112 as mask until the polysilicon layer 108 is exposed.
In FIG. 1H, the exposed polysilicon layer 108 is removed until the gate oxide layer 107, the field oxide layer 101, and the inter-poly oxide layer 106 are exposed. The photo-resist layer 112 is removed to form a gate 114 comprising a part of the tungsten silicide layer 110 and a part of the polysilicon layer 108, and a top electrode 110a comprising the other parts of the tungsten silicide layer 110 and polysilicon layer 108. A capacitor 116 is thus formed to comprise the bottom electrode 103a, the inter-poly oxide layer 106, and the top electrode 110a.
In the above method, since the silicon lattice structures of the silicon substrate and the polysilicon layer are different, a thickness ratio about 1 to 2 is resulted instead of obtaining an identical thickness of the gate oxide layer 107 and the inter-poly oxide layer 106. The thickness of the gate oxide layer 107 is thus difficult to control as required. The capacitor 116 is formed by forming and patterning two polysilicon layers, respectively. The fabrication process is lengthy and complicated, so that the fabrication cost is increased.